B 02 4 8 40 1 2 3 5 6 7 9 00 01 10 11 "entity backbone is generic( gp_master: boolean := TRUE ) port (clk : in std_logic -- interface clock reset clk100m reset100 clk330m reset330 reset_img rst refclk_1d refclk_1e refclk_1f clk1ms locked_gp out slotid slotid_type eth_open_port0_t Local Read ports LPR ----------------------- lpri read_req_array (others => empty_local_read_req) lpro read_ack_array Write LPW lpwi write_req_array empty_local_write_req) lpwo write_ack_array memory MPR ------------------- mpro dram_read_req_array mpri dram_read_ack_array empty_dram_read_ack) MPW mpwo dram_write_req_array mpwi dram_write_ack_array empty_dram_write_ack) readout write brdi dram_write_req_array3 empty_dram_write_req) brdo dram_write_ack_array3 crazy bus crazyi crazy_bus empty_crazy crazyo crazy_bus serial interconnects s_rx std_logic_vector(7 downto 0) s_tx gp_rx std_logic_vector(NR_PCHANS-1 gp_tx gp_nmodpresent: unsigned(NR_PCHANS-1 gp_rx_loss: enc_tx: enc_dis_type enc_rx: rcf_pending: status --------- online unsigned(1 led_tx online_gp led_tx_gp reconfigo avalon_out_type reconfigi avalon_in_type empty_avalon_in end entity backbone architecture rtl of signal lpri_int: read_req_array lpro_int: lpwi_int: write_req_array lpwo_int: mpro_int: mpri_int: dram_read_ack_array mpwo_int: mpwi_int: dram_write_ack_array statusl statusr: unsigned(63 status_gp: gp_status_type wrstatusl wrstatusr wrerrorflag: wrerrorflag_gp rdstatus_gp: crazyom: d0 din dout: unsigned(15 address: unsigned(26 re we: errorflag: unsigned(31 type errorflag_gp_type array(12 0) !! bits before channel!! errorflag_gp: errorflag_gp_type reconfigi_bb reconfigi_all: avalon_in_type reconfig_reset_t reconfig_req_t reconfig_ack_t: reconfig_cmd reconfig_rdata: unsigned(7 reconfig_status: mess_req: unsigned(3 mess_ack: enc_dis_ports (EP_BBL EP_BBR EP_GP EP_ETH) enc_dis_array_type array(enc_dis_ports) enc_in enc_out: enc_dis_array_type begin connect masters and slaves g1: for i READ_PORTS generate if /= RP_BB lpri_int(i) <= lpri(i) lpro(i) lpro_int(i) else empty_local_read_ack g1 g2: WRITE_PORTS WP_BBL WP_BBR WP_GP lpwi_int(i) lpwi(i) lpwo(i) lpwo_int(i) empty_local_write_ack g2 g3: DRAM_PORTS DP_BB DP_REGS DP_GP mpri_int(i) mpri(i) mpro(i) mpro_int(i) mpwi_int(i) mpwi(i) mpwo(i) mpwo_int(i) empty_dram_read_req empty_dram_write_req g3 dram read arbiter u1: work.dramreadarb map( clk clk reset my_address slotid.id lpri_int lpro_int mpro_int mpri_int dra_fifo_ef errorflag(13) dra_fifo_ovf errorflag(14) u2: work.dramwritearb lpwi_int lpwo_int mpwo_int mpwi_int errors dra_lpwi_ovf errorflag(15) master slave u3: work.bbport clk100m reset100 clk330m reset330 refclk1d refclk_1d clk1ms slotid eth_open_port0_t bsri mpro_int(DP_BB) bsro mpri_int(DP_BB) bswi mpwo_int(DP_BB) bswo mpwi_int(DP_BB) bmro lpri_int(RP_BB) bmri lpro_int(RP_BB) left bmwol lpwi_int(WP_BBL) bmwil lpwo_int(WP_BBL) right bmwor lpwi_int(WP_BBR) bmwir lpwo_int(WP_BBR) bb links bbo s_tx bbi s_rx encoder enc_rxl enc_in(EP_BBL) enc_txl enc_out(EP_BBL) enc_rxr enc_in(EP_BBR) enc_txr enc_out(EP_BBR) statusl statusr statusr wrstatusl wrstatusr online led_tx rcf_pending rcf_pending --detected phy_rx_fifo_ovf errorflag(0) phy_packet_no_head_tx errorflag(1) phy_dropped_tx errorflag(16) phy_tx_fifo_full errorflag(18) bmwol_buf_ovf errorflag(3) bmwor_buf_ovf errorflag(6) bmri_buf_ff errorflag(8) bmria_buf_ff errorflag(9) bmria_buf_ef errorflag(10) bswi_buf_ff errorflag(11) bswia_buf_ff errorflag(12) reconfigo reconfigi_bb errorflag(2) '0' errorflag(4) errorflag(5) errorflag(7) errorflag(17) gp0: work.gpports generic gp_master) clk100M reset_img rst gxb_refclk refclk_1f locked locked_gp my_dram PORT_ADDRESS_START(DP_GP) mpro_int(DP_GP) mpri_int(DP_GP) mpwo_int(DP_GP) mpwi_int(DP_GP) ---- --bmro lpri_int(RP_GP) --bmri lpro_int(RP_GP) bmwo lpwi_int(WP_GP) bmwi lpwo_int(WP_GP) unit brdi brdo gp gp_tx gp_rx gl_nmodpresent gp_nmodpresent gl_rx_loss gp_rx_loss enc_rx enc_in(EP_GP) enc_tx enc_out(EP_GP) status_gp rdstatus rdstatus_gp online_gp led_tx_gp detected errorflag_gp(0) errorflag_gp(1) errorflag_gp(3) errorflag_gp(4) bmwo_buf_ovf errorflag_gp(6) errorflag_gp(8) errorflag_gp(9) errorflag_gp(10) errorflag_gp(11) errorflag_gp(12) errorflag_gp(2) '0') errorflag_gp(5) errorflag_gp(7) u4: work.crazy_master mpwo_int(DP_REGS) mpwi_int(DP_REGS) mpro_int(DP_REGS) mpri_int(DP_REGS) crazy_in crazyi crazy_out crazyom only used info u5: work.crazy_slave map (MY_ADDRESS X) ( crazyom crazyo mess_req mess_req length X aout address we we dout dout re din merge signals there are possible sources: EP_BBL EP_GP a source that provides change on up_cnt key = considered legitimate send to all destinations except do not feed back backplane penc:process(clk) upd_type array(ENC_DIS_PORTS) variable upd updd: upd_type keyd_type keyd keydd keyddd zerod zerodd: keyd_type ok_type boolean ok: ok_type rising_edge(clk) then ENC_DIS_PORTS loop ok(i) j enc_out(j) enc_in(i) copy outputs (i j) enc_out(j).up_cnt don't enc_out(j).zero upd(i) use delayed version make sure other stable zerod(i) if loop (upd(i) updd(i) or zerod(i) zerodd(i)) keyd(i) '1' keydd(i) keyddd(i) '1' keyddd keydd keydd keyd updd upd zerodd zerod upd(i) enc_in(i).up_cnt to_std_logic(enc_in(i).key enc_in(i).zero enc_out empty_enc_dis) ok false) process penc enc_out(EP_ETH) enc_in(EP_ETH) enc_rx errorflag(31 20+dp_to_nat(DRAM_PORTS'right)) g4: errorflag(dp_to_nat(i)+19) mpwi_int(i).ovf (26 19) g4 p1:process(clk) errorflag1: errorflag1_gp_type array(NR_PCHANS-1 unsigned(12 errorflag1_gp: errorflag1_gp_type online_gp1 online_gp2 online_gp3: online_gp_cnt: unsigned(14 online_gp_cnt_d: reconfig_ack_t1 reconfig_ack_t2 reconfig_ack_t3: wrerrorflag case address(9 when 10X reconfig_cmd(7 dout(7 reconfig_cmd(7) reconfig_reset_t reconfig_reset_t reconfig_req_t reconfig_req_t others case wrerrorflag_gp NR_PCHANS-1 2) i+12 wrerrorflag_gp(i) rdstatus_gp mess_ack d0 7) 0x0 - 0xFF address(6 0x0000: BBSTSLEFT 7X statusl(15 statusl(31 16) statusl(47 32) --d0 statusl(63 48) 0x0008: BBSTSRIGHT statusr(15 statusr(31 statusr(47 statusr(63 0x0010: BBERRORFLAGS errorflag1(15 errorflag1(31 0x0080: RECONFIG d0(1 reconfig_status 0x0020 0x0040: BBSSTS_GP0-4 to_integer(address(6 2)) 4+i address(1 status_gp(i)(15 status_gp(i)(31 status_gp(i)(47 resize(status_gp(i)(55 48) 0x0060 BBERRORFLAGS_GP0-4 12+i resize(errorflag1_gp(i) rdstatus_gp(i) elsif 0x200 0x2FF address(0) '0' resize(online_gp3 message d0(7 reconfig_rdata TODO: too late? d0 online_gp_cnt(online_gp_cnt'high) online_gp_cnt_d X reconfig_ack_t3 reconfig_ack_t2 These can be missed changes coincide online_gp_cnt(online_gp_cnt'high) Filter noise avoid flooding online_gp2 online_gp3 online_gp_cnt + 1 online_gp2 online_gp1 online_gp1 online_gp reconfig_ack_t2 reconfig_ack_t1 reconfig_ack_t1 reconfig_ack_t errorflag1 errorflag 12 errorflag1_gp(i)(j) errorflag_gp(j)(i) errorflag1_gp '0')) p1 reconfigi_all.readdata reconfigi_bb.readdata unsigned(reconfigo.address(15 13)) reconfigi.readdata reconfigi_all.waitrequest reconfigi_bb.waitrequest reconfigi.waitrequest reconfigi_all.readdatavalid u6: work.reconfig Crazy address reconfig_ack_t reconfig_ack_t reconfigi_all reconfig_cmd reconfig_status reconfig_status reconfig_rdata rtl"